The present invention relates to a multiplier for converting a clock signal to a higher-frequency clock signal and in particular to a multiplier comprising a plurality of series-connected one-shots.
During design of integrated circuits and during quality control of integrated circuit production, it is common for circuit testing equipment to be connected to an integrated circuit for driving a circuit and observing the resultant output signals. Many modern integrated circuits are designed to operate at high clock signal frequencies such as 0.2 gigahertz (GHz) or more. Thus, it is desirable when testing such a chip to provide a high frequency clock signal. However, much commonly-available testing equipment has a maximum clock period of about 40 nsec., and thus is incapable of driving a chip at a high frequency clock signal. Although some specialty test equipment may be available for high frequency testing, the cost and availability of such specialty test equipment makes it impractical to use specialty test equipment for, e.g., quality control testing or field testing of installed equipment. The typically available test equipment provides a clock signal with a frequency of about 25 megahertz (MHz) or less.
Accordingly, there is a need for a system for testing integrated circuits at a high clock frequency, approaching the normal operating clock frequency for the circuit, without requiring expensive and not readily available high-frequency test equipment.